The main limitation of the 8-bit microprocessor was
-Low Speed
-Low memory addressing capability
-Less powerful instruction set
-A limited number of General Purpose Register
All these limitations were later rectified in 8086.

Architecture- Supports a 16 bit ALU, a set of 16-bit registers and provides the segmented memory addressing capability, powerful interrupt structure, fetched instruction queue for overlapped fetching and execution, etc.

Architecture divided into two parts
-Bus interface unit- Contains the circuit for physical address calculations and a pre-decoding instruction byte queue.

Responsible for establishing communication with external devices and peripherals including memory via the bus.

The complete physical address which is 20 bit long is generated using the segment and offset register, each 16 bit long.
It has to address the capability of 1M byte memory locations.

Generation of physical address
Content of segment register is shifted left bit-wise four times and this result, the content of an offset register is added to produce 20-bit physical address.

The offset address values are from 0000H and FFFFH so that the physical addresses range from 00000H to FFFFFH.

For example, if the segment register is 1005H and the offset if 5555H, then the physical address is will be 1005*10+5555=155A5H

A maximum of 64K locations may be accommodated in the segment.

The segment register indicates the base address of a particular segment, while the offset indicates the distance of the required memory location in the segment from the base address.

The segment address value is to be taken from an appropriate segment register while the content of IP, BX, SI, DI, SP, BP depending on the address mode.

In 8085, once the op-code is fetched and decoded, the external bus remains free for some time while the processor internally executes the instruction.
In 8086, the empty time slot is utilized to achieve the overlapped fetch and execution cycles.
The external bus is used to fetch the machine code of the next instruction and arrange it in a queue known as pre-decoded instruction byte queue.
It is 6 bytes long and works on FIFO.

While the op-code is fetched by the interface unit, the execution unit executes the previously decoded instruction concurrently.
The Interface unit along with Execution forms a pipeline.





-Execution Unit- contains the register set of 8086 except segment register and IP.
-16-bit ALU to perform arithmetic and logical operation.

Register organization of 8086.
8086 have a general-purpose register and special-purpose registers.
All of them are 16-bit register.

The register is categorized into four groups
General data register – AX, BX, CX, and DX are the general-purpose register.

Segment Register- CS , SS , DS and ES/
Flag Register – Flag and PSW
Pointer and Index Register- SP, BP ,SI , DI and IP.

AX is the accumulator
BX – Offset Storage
CX- Counter
DX- to store the data

Unlike 8085, 8086 addresses segmented memory.
The complete 1 megabytes which the 8086 addresses, is divided into 16 logical segments.
Each segment thus contains 64K bytes of memory.
There are 4 segment registers
Code segment register (CS) -> Code,
Data segment register (DS) -> Data,
Extra segment register (ES) ->Data,
Stack segment register (SS) ->Stack related

CPU uses the stack for temporary data.


Pointers and Index registers:
• The pointers contain offset within the particular segment.
• The pointers IP, BP, and SP usually contain offsets
The index registers are used as general-purpose registers as well as for offset storage in case of indexed.

The register SI is generally used to store the offset of the source data in the data segment while the register DI is used to store the offset of the destination in data or extra segment.

Index register are particularly useful for string manipulations.

An assembly language program model of 8086 is as follows ASSUME DS: DATA, CS: CODE
DATA SEGMENT. (Declaration of data variables, constants, etc).
DATA ENDS
CODE SEGMENT
START
:MOV AX,DATA
MOV DS,AX.
.
CODE ENDS
END START
END

The main advantage of the segmented memory
-Allows the memory capacity to be 1Mbytes although the actual addresses to be handled are of a 16-bit size.
-Allows the placing of the code, data, and stack portions of the same program in different parts of memory for data and code protection.
– Permits a program and/or its data to be put into different areas of memory each time the program is executed ie provision for relocation is done.



Flag Register
8086 has 16-bit flag register which is divided into two parts, viz
-Condition Flag
-Machine Control flags

The condition code flag register is the lower byte of the 16bit flag register along with the overflow flag.

The control flag register is the higher byte of the flag register of 8086.

It contains three flags, viz
Direction flag (D)
Interrupt flag (I)
Trap Flag (T)

Image result for flag register of 8086

When the Trap flag is triggered the processor enters into single-step execution mode.

I – Interrupt Flag – If this flag is set, the maskable interrupts are recognized by the CPU, otherwise they are ignored.

D – Direction flag – This flag is used by string manipulations instruction. If this flag bit is 0, the string is processed beginning from the lowest address to the highest address ie auto-increment mode. Otherwise, the string is processed from the highest address towards the lowest address ie auto decrement mode.

ZF- Zero Flag- Set if the result is zero; otherwise,
add 0,0 ; ZF=1

Sign Flag (SF)
– set when the result of an operation is negative that is if the MSB of the result is 1.

sub 0000000000, 0000000001 ; -> 1111111111
SF flag will be one.

Parity Flag: set if the low-order eight bits of result contains an even number of “1” bits;
add 11010, 1; -> result is 11011 -> 4 bits are ‘1’ ->PF=1

add 11000, 1; -> result is 11001 -> 3 bits are ‘1’ ->PF=1


Auxillary Flag if there is carry from lower nibble to higher nibble or if there is borrow from higher nibble to lower nibble then AF is set to 1.

The microprocessor 8086 is a 16 bit CPU available in 3 clock rates 5,8 and 10 MHz, packed in a 40 pin CERDIP or plastic package